The present invention relates to a comparator that allows for high frequency analog signal comparison. In particular, the exemplary embodiments relate to eliminating the input frequency dependent and statistical offsets that affect the trigger point, response time of the comparator and group delay of the comparator.
The purpose of an analog-to-digital converter (ADC) is to convert an analog signal into a digital representation of the analog signal. One of the building blocks of an ADC is a comparator that compares an input signal to a reference signal. An ADC may have a dedicated front-end sample and hold amplifier (SHA) to alleviate the timing requirements in the front-end that have to be met while processing, especially, high input frequencies. For example, in a pipelined ADC, a first stage may include a multiplying-digital-to-analog-converter (MDAC1) and a first-stage sub-ADC, which is typically a flash ADC (Flash1). The MDAC1 and Flash1 must have a certain clock and analog input signal skew limits. The clock and the skew limits allow the ADC to sustain certain target performance at the high input frequencies. However, a dedicated front-end SHA increases power consumption, noise, and chip area. Therefore, avoiding a front-end SHA can be advantageous to reduce power consumption, noise and die cost. The present embodiments also mitigate the design challenges related to matching the Flash1 group delay to MDAC1 group delay.
FIG. 1 illustrates a conventional comparator. The comparator 100 includes a pre-amplifier stage 110 and a latch stage 120. The pre-amplifier stage 110 is an operational transconductance amplifier (OTA) that receives a differential input voltage signal VIN, and generates a differential output current. The latch stage 120 includes a pair of inverters connected in parallel, but in opposite polarity to one another (cross-coupled) and a reset switch 125 is also connected in parallel to the inverters at the output of the comparator 100.
The comparator 100 has two distinct operating phases based on the state of the latch switch; acquire/reset phase and a latch/regeneration phase. The comparator is in the acquire/reset phase when the latch switch is closed, and it is in the latch/regeneration phase when the reset switch is opened. In operation, the differential input voltage signal VIN applied to the differential inputs of the pre-amplifier stage 110 is converted to differential currents. The generated differential currents are proportional to the difference of the applied differential VIN voltages. The differential currents are provided to the latch stage 120. The pair of inverters 121 and 122 responds to the provided differential currents, and output a voltage equivalent of either logic “1” or “0” when the reset switch is turned off. During the latch phase, when the reset switch is open, the output, Vout, is a digital representation of the polarity of the input signal at the instant the reset switch is opened. The arrangement of the inverters 121 and 122 serves to maintain the state, or output voltage, at a particular value until the latch is reset. To reset the latch stage 120, the reset latch switch 125 is closed to short the inputs to the outputs of the inverters 121 and 122, and the latch 120 is brought to its trip point. When the latch is reset, it is kept at its trip point and it is ready to respond to the differential signal provided by the preamplifier. As soon as the reset switch opens, the latch starts to regenerate and produce a digital representation of the polarity of the input signal. However, the regeneration is not instantaneous. In other words, the latch cannot produce a digital representation of the polarity of the input signal instantaneously. Consequently, while the latch 120 is trying to produce a digital representation, the preamplifier 110 continues to supply a signal proportional to the input signal to the latch. Since the input signal continues to influence the latch 120 during the latch phase (when the latch switch is open), if the input signal changes substantially before the latch can produce a valid digital output, the input signal can influence the latch's decision. Therefore, a fast changing input can alter the trip point of the comparator. This results in an input-frequency-dependent trip point or offset of the latch.
One way to compensate for the input-frequency dependency of the trip point is to isolate the latch circuit 120 from the preamplifier 110 during the latch/regeneration phase. This can be done with isolation switches. By using isolation switches, the input cannot influence the latch core during the latch/regeneration phase, and the latch's decision is not altered by the input during the latch/regeneration phase. The latch's decision is based on the input value at the time the latch switch opens (or turns off). However, the introduction of isolation switches between the preamplifier 110 and the latch 120 core worsens another type of offset, called statistical offset. Statistical offset is a result of random shifts in device parameters during fabrication. Appropriately sizing the devices and maximizing the voltage gain of the preamplifier reduces the input referred statistical offset. However, the reduction in statistical offset may not be adequate, or the device sizes may have to be optimized to meet other design specifications.
There is a need for a comparator design suitable for comparing high frequency input signals that does not have a large amount of offset group delay, and has a fast response time. The inventor recognized a solution to the above problems as illustrated in the following embodiments.